In the current flip-chip technology, electrode pads are formed on a surface of a semiconductor integrated circuit (IC) chip and corresponding conductive pads are formed on an organic package substrate, such that solder bumps or other conductive adhesive materials can be bonded between the electrode pads of the chip and the conductive pads of the package substrate so as to allow an active surface of the chip to be mounted on the package substrate in a face-down manner. The solder bumps or other conductive adhesive materials are used to provide electrically input/output connections and mechanical connections between the chip and the package substrate.
After a subsequent packaging process of the package substrate, the chip and passive components is performed, a plurality of solder balls are usually mounted on a surface of the substrate to electrically connect the substrate to an external electronic device. In order to effectively mount the solder balls on the substrate, a solder material for implanting the solder balls needs to be in advance applied on the conductive pads of the substrate.
Stencil printing technology is commonly employed to deposit the solder material on the substrate. Referring to FIG. 1, the currently used stencil printing technology mainly involves providing a package substrate 10 having a solder mask layer 11 (such as an insulating resin material) and a plurality of conductive pads 12 for defining locations of a solder material such as solder paste (not shown) on a surface of the package substrate 10. A stencil 13 having a plurality of grids 13a is disposed on the package substrate 10, and the solder material is placed on the stencil 13. Then, a roller 14 is used to repeatedly roll on the stencil 13 or a spraying process is performed to apply the solder material on the conductive pads 12 through the grids 13a so as to form solder (not shown) on the conductive pads 12 after removing the stencil 13. Subsequently, under a condition with a reflow temperature at which the solder would melt, the solder is subjected to a reflow-soldering process to form a soldered element (not shown) on each of the conductive pads 12 of the substrate 10 to be electrically connected to an external electronic device.
In practical implementation, along with the blooming development of various portable devices in the fields of communication, networking and computing, there have been provided different types of packages such as ball grid array (BGA) package, flip-chip package, chip size package (CSP) and multi chip module (MCM), which are characterized with a miniaturized integrated circuit (IC) area, high density and multiple leads, and have become mainstream products on the market for use with highly effective chips such as a microprocessor, a chip set and a graphic chip so as to achieve higher speed operations. However, those package structures must have a reduced width of circuits and a reduced size of conductive pads on substrates thereof. When a pitch between the adjacent conductive pads keeps being reduced, since each of the conductive pads is partly covered by a protective layer formed on the substrate, the size of the conductive pads exposed from the protective layer would further be reduced. This thus causes an alignment problem during subsequent formation of solder bumps on the exposed conductive pads using the stencil printing technology. Moreover, in consideration of the occupied space and the height of the protective layer, the size of grids or openings of the stencil should be accordingly decreased, thereby making fabrication of such stencil become difficult and also increasing the fabrication costs of the stencil. This may further make the solder material hard to pass through the small grids of the stencil and lead to difficulty in fabrication.
Furthermore, the production accuracy of the solder material depends on not only the precise size of the stencil but also the frequency and cleanness of performance of the stencil printing process. Since the solder material has certain viscosity, the more times of printing being performed, the more residues of solder material remain on walls of the grids of the stencil. This causes the amount and shape of the solder material used and formed in the next printing process to be different from those of the predetermined design. Therefore, the stencil needs to be wiped or cleaned after performing certain times of the printing process during practical operation; otherwise, the shape and size of the solder material would become inaccurate or incorrect, and thus convenience and reliability in fabrication are degraded.
Accordingly, an electroplating process is alternatively employed in place of the above stencil printing technology to form the solder material. However, the stencil printing technology and the electroplating process both require a large amount of the solder material to be mounted on the conductive pads to achieve a sufficient height of the solder material for being electrically connected to the external electronic device and to ensure bondability for a subsequent soldering process. This not only increases the costs of the solder material but also makes the fabrication time-consuming as electroplating of the solder material requires a longer period of time. Further, usage of the large amount of solder material needs relatively higher material costs and thus effectively increases the fabrication costs.